A Novel Low-Power Synchronous Preamble Data Line Chip Design for Oscillator Control Interface

A Novel Low-Power Synchronous Preamble Data Line Chip Design for Oscillator Control Interface

In this paper, a novel low-power synchronous preamble data line protocol chip design for serial communication is proposed. The serial communication only uses two wires, chip select (CS) and secure digital (SD), to transmit and receive data between two devices. The proposed protocol aims to use a few...

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書目詳細資料
Main Authors:	Chen, Shih-Lun, Chi, Tsun-Kuang, Tuan, Min-Chun, Chen, Chiung-An, Wang, Liang-Hung, Chiang, Wei-Yuan, Lin, Ming-Yi, Abu, Patricia Angela R
格式:	text
出版:	Archīum Ateneo 2020
主題:	SPI digital signal process communication protocols CMOS digital integrated circuit field-programmable gate array (FPGA) electronic device measurement and very-large-scale integration (VLSI) Computer Sciences Databases and Information Systems
在線閱讀:	https://archium.ateneo.edu/discs-faculty-pubs/314 https://archium.ateneo.edu/cgi/viewcontent.cgi?article=1285&context=discs-faculty-pubs
標簽:	添加標簽沒有標簽, 成為第一個標記此記錄!
機構:	Ateneo De Manila University

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