Hardware Implementation of an Iterative Parallel Scheduler for Optical Interconnection Networks

This paper proposes an iterative parallel scheduler for optical interconnection networks based on the longest queue first algorithm, presents an optimized hardware implementation in commercial FPGA boards, and experimentally assess its performance.

Saved in:

Bibliographic Details
Main Authors:	Corvera, Jan Alain, Dumlao, Samuel Matthew G, Reyes, Rosula SJ, Castoldi, Piero, Andriolli, Nicola, Cerutti, Isabella
Format:	text
Published:	Archīum Ateneo 2016
Subjects:	Algorithms Field programmable gate arrays Optical networks Electrical and Computer Engineering
Online Access:	https://archium.ateneo.edu/ecce-faculty-pubs/56 https://www.osapublishing.org/abstract.cfm?uri=Networks-2016-NeM3B.4
Tags:	Add Tag No Tags, Be the first to tag this record!
Institution:	Ateneo De Manila University

id	ph-ateneo-arc.ecce-faculty-pubs-1055
record_format	eprints
spelling	ph-ateneo-arc.ecce-faculty-pubs-10552020-08-12T06:51:29Z Hardware Implementation of an Iterative Parallel Scheduler for Optical Interconnection Networks Corvera, Jan Alain Dumlao, Samuel Matthew G Reyes, Rosula SJ Castoldi, Piero Andriolli, Nicola Cerutti, Isabella This paper proposes an iterative parallel scheduler for optical interconnection networks based on the longest queue first algorithm, presents an optimized hardware implementation in commercial FPGA boards, and experimentally assess its performance. 2016-01-01T08:00:00Z text https://archium.ateneo.edu/ecce-faculty-pubs/56 https://www.osapublishing.org/abstract.cfm?uri=Networks-2016-NeM3B.4 Electronics, Computer, and Communications Engineering Faculty Publications Archīum Ateneo Algorithms Field programmable gate arrays Optical networks Electrical and Computer Engineering
institution	Ateneo De Manila University
building	Ateneo De Manila University Library
continent	Asia
country	Philippines Philippines
content_provider	Ateneo De Manila University Library
collection	archium.Ateneo Institutional Repository
topic	Algorithms Field programmable gate arrays Optical networks Electrical and Computer Engineering
spellingShingle	Algorithms Field programmable gate arrays Optical networks Electrical and Computer Engineering Corvera, Jan Alain Dumlao, Samuel Matthew G Reyes, Rosula SJ Castoldi, Piero Andriolli, Nicola Cerutti, Isabella Hardware Implementation of an Iterative Parallel Scheduler for Optical Interconnection Networks
description	This paper proposes an iterative parallel scheduler for optical interconnection networks based on the longest queue first algorithm, presents an optimized hardware implementation in commercial FPGA boards, and experimentally assess its performance.
format	text
author	Corvera, Jan Alain Dumlao, Samuel Matthew G Reyes, Rosula SJ Castoldi, Piero Andriolli, Nicola Cerutti, Isabella
author_facet	Corvera, Jan Alain Dumlao, Samuel Matthew G Reyes, Rosula SJ Castoldi, Piero Andriolli, Nicola Cerutti, Isabella
author_sort	Corvera, Jan Alain
title	Hardware Implementation of an Iterative Parallel Scheduler for Optical Interconnection Networks
title_short	Hardware Implementation of an Iterative Parallel Scheduler for Optical Interconnection Networks
title_full	Hardware Implementation of an Iterative Parallel Scheduler for Optical Interconnection Networks
title_fullStr	Hardware Implementation of an Iterative Parallel Scheduler for Optical Interconnection Networks
title_full_unstemmed	Hardware Implementation of an Iterative Parallel Scheduler for Optical Interconnection Networks
title_sort	hardware implementation of an iterative parallel scheduler for optical interconnection networks
publisher	Archīum Ateneo
publishDate	2016
url	https://archium.ateneo.edu/ecce-faculty-pubs/56 https://www.osapublishing.org/abstract.cfm?uri=Networks-2016-NeM3B.4
_version_	1728621357200048128

Hardware Implementation of an Iterative Parallel Scheduler for Optical Interconnection Networks

Similar Items