Multifingers capacitances modeling of 65-Nm CMOS transistor by unit cell method

Multifingers capacitances modeling of 65-Nm CMOS transistor by unit cell method

The multifingers' parasitic capacitances modeling of 65-nm CMOS transistors for millimeter-wave application is presented. The modeling is based on simulation approach, which is done by building the devices true dimension in high-frequency structure simulator environment. The material properties...

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Main Authors: Agung, Alit Apriyana Anak, Zhang, Yue Ping
Other Authors: School of Electrical and Electronic Engineering
Format: Article
Language:English
Published: 2013
Subjects:
DRNTU::Engineering::Electrical and electronic engineering
Online Access:https://hdl.handle.net/10356/102842
http://hdl.handle.net/10220/16915
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-1028422020-03-07T14:00:36Z Multifingers capacitances modeling of 65-Nm CMOS transistor by unit cell method Agung, Alit Apriyana Anak Zhang, Yue Ping School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering The multifingers' parasitic capacitances modeling of 65-nm CMOS transistors for millimeter-wave application is presented. The modeling is based on simulation approach, which is done by building the devices true dimension in high-frequency structure simulator environment. The material properties of the devices as given by the foundry are used during simulation and then full electromagnetic simulations are carried out to extract the Y-parameters of the model. Unit-cell parameters extraction method is carried out in order to save memory and simulation time. In this case, the multifinger transistors are divided into unit-cells and then the parasitic capacitances of the unit-cells are calculated from the extracted Y-parameter. Based on linear scaling, the parasitic capacitance of the multifingers transistor can be obtained with good accuracy (less than 5% error). 2013-10-25T06:48:06Z 2019-12-06T21:01:04Z 2013-10-25T06:48:06Z 2019-12-06T21:01:04Z 2012 2012 Journal Article Agung, A. A. A., & Zhang, Y. P. (2012). Multifingers capacitances modeling of 65-Nm CMOS transistor by unit cell method. International Journal of RF and Microwave Computer-Aided Engineering, 22(3), 297-307. https://hdl.handle.net/10356/102842 http://hdl.handle.net/10220/16915 10.1002/mmce.20576 en International journal of RF and microwave computer-aided engineering © 2012 Wiley Periodicals, Inc.
institution Nanyang Technological University
building NTU Library
country Singapore
collection DR-NTU
language English
topic DRNTU::Engineering::Electrical and electronic engineering
spellingShingle DRNTU::Engineering::Electrical and electronic engineering
Agung, Alit Apriyana Anak
Zhang, Yue Ping
Multifingers capacitances modeling of 65-Nm CMOS transistor by unit cell method
description The multifingers' parasitic capacitances modeling of 65-nm CMOS transistors for millimeter-wave application is presented. The modeling is based on simulation approach, which is done by building the devices true dimension in high-frequency structure simulator environment. The material properties of the devices as given by the foundry are used during simulation and then full electromagnetic simulations are carried out to extract the Y-parameters of the model. Unit-cell parameters extraction method is carried out in order to save memory and simulation time. In this case, the multifinger transistors are divided into unit-cells and then the parasitic capacitances of the unit-cells are calculated from the extracted Y-parameter. Based on linear scaling, the parasitic capacitance of the multifingers transistor can be obtained with good accuracy (less than 5% error).
author2 School of Electrical and Electronic Engineering
author_facet School of Electrical and Electronic Engineering
Agung, Alit Apriyana Anak
Zhang, Yue Ping
format Article
author Agung, Alit Apriyana Anak
Zhang, Yue Ping
author_sort Agung, Alit Apriyana Anak
title Multifingers capacitances modeling of 65-Nm CMOS transistor by unit cell method
title_short Multifingers capacitances modeling of 65-Nm CMOS transistor by unit cell method
title_full Multifingers capacitances modeling of 65-Nm CMOS transistor by unit cell method
title_fullStr Multifingers capacitances modeling of 65-Nm CMOS transistor by unit cell method
title_full_unstemmed Multifingers capacitances modeling of 65-Nm CMOS transistor by unit cell method
title_sort multifingers capacitances modeling of 65-nm cmos transistor by unit cell method
publishDate 2013
url https://hdl.handle.net/10356/102842
http://hdl.handle.net/10220/16915
_version_ 1681040212613922816

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