Multifingers capacitances modeling of 65-Nm CMOS transistor by unit cell method

• Main Authors: Agung, Alit Apriyana Anak, Zhang, Yue Ping
• 其他作者: School of Electrical and Electronic Engineering
• 格式: Article
• 語言: English
• 出版: 2013
• 主題: DRNTU::Engineering::Electrical and electronic engineering
• 在線閱讀: https://hdl.handle.net/10356/102842; http://hdl.handle.net/10220/16915
• 機構: Nanyang Technological University

The multifingers' parasitic capacitances modeling of 65-nm CMOS transistors for millimeter-wave application is presented. The modeling is based on simulation approach, which is done by building the devices true dimension in high-frequency structure simulator environment. The material properties...