Multifingers capacitances modeling of 65-Nm CMOS transistor by unit cell method
The multifingers' parasitic capacitances modeling of 65-nm CMOS transistors for millimeter-wave application is presented. The modeling is based on simulation approach, which is done by building the devices true dimension in high-frequency structure simulator environment. The material properties...
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| Main Authors: | , |
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| Other Authors: | |
| Format: | Article |
| Language: | English |
| Published: |
2013
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| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/102842 http://hdl.handle.net/10220/16915 |
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| Institution: | Nanyang Technological University |
| Language: | English |
| Summary: | The multifingers' parasitic capacitances modeling of 65-nm CMOS transistors for millimeter-wave application is presented. The modeling is based on simulation approach, which is done by building the devices true dimension in high-frequency structure simulator environment. The material properties of the devices as given by the foundry are used during simulation and then full electromagnetic simulations are carried out to extract the Y-parameters of the model. Unit-cell parameters extraction method is carried out in order to save memory and simulation time. In this case, the multifinger transistors are divided into unit-cells and then the parasitic capacitances of the unit-cells are calculated from the extracted Y-parameter. Based on linear scaling, the parasitic capacitance of the multifingers transistor can be obtained with good accuracy (less than 5% error). |
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