Low power CMOS memory circuit design

• المؤلف الرئيسي: Foo, Chee Heng
• مؤلفون آخرون: Lau K T
• التنسيق: Final Year Project
• اللغة: English
• منشور في: Nanyang Technological University 2020
• الموضوعات: Engineering::Electrical and electronic engineering::Integrated circuits
• الوصول للمادة أونلاين: https://hdl.handle.net/10356/138635

Two novel SRAM is proposed and simulated with TSMC 40nm technology. Both novel 10T SRAM is designed to be used under low power supply, with features such as low power consumption and high reading static noise margin. Both proposed SRAM can operate under supply voltage as low as 0.31V. Under this sup...