A high-speed 2-bit/cycle SAR ADC with time-domain quantization

• Main Authors: Qiu, Lei, Yang, Chuanshi, Wang, Keping, Zheng, Yuanjin
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2020
• Subjects: Engineering::Electrical and electronic engineering; 2 Bit/cycle; Analog-to-digital Converter (ADC)
• Online Access: https://hdl.handle.net/10356/142511
• Institution: Nanyang Technological University

This brief presents a 2-bit/cycle successive approximation register (SAR) analog-to-digital converter (ADC) with time-domain quantization, which only needs one capacitive digital-to-analog converter (DAC) array. A duplicated dynamic comparator is adopted to generate the time references. To quantize the time value, a dynamic latch-based high precision time-domain comparator is proposed. Moreover, a redundancy technique is utilized to overcome the effect of nonideal factors, such as incomplete DAC settling, reference scale mismatch, and offset of comparators. A design example of 9-bit 700 MS/s SAR ADC in 65-nm CMOS technology is presented. Simulation results show that with a differential 600-mVp-p input, the spurious free dynamic range at Nyquist input is above 65 dB. The simulated effective number of bit is up to 8.3 bits at 10-MHz input with the presence of noise and mismatches calibration.