A high-speed 2-bit/cycle SAR ADC with time-domain quantization
This brief presents a 2-bit/cycle successive approximation register (SAR) analog-to-digital converter (ADC) with time-domain quantization, which only needs one capacitive digital-to-analog converter (DAC) array. A duplicated dynamic comparator is adopted to generate the time references. To quantize...
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Main Authors: | , , , |
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Other Authors: | |
Format: | Article |
Language: | English |
Published: |
2020
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Subjects: | |
Online Access: | https://hdl.handle.net/10356/142511 |
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Institution: | Nanyang Technological University |
Language: | English |
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