A high-speed 2-bit/cycle SAR ADC with time-domain quantization

This brief presents a 2-bit/cycle successive approximation register (SAR) analog-to-digital converter (ADC) with time-domain quantization, which only needs one capacitive digital-to-analog converter (DAC) array. A duplicated dynamic comparator is adopted to generate the time references. To quantize...

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Main Authors: Qiu, Lei, Yang, Chuanshi, Wang, Keping, Zheng, Yuanjin
其他作者: School of Electrical and Electronic Engineering
格式: Article
語言:English
出版: 2020
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在線閱讀:https://hdl.handle.net/10356/142511
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機構: Nanyang Technological University
語言: English