Low power CMOS clocked storage elements

Modern Systems-on-chips (SoCs) pack tens of millions of gates in a minuscule area which has resulted in the power consumption of chips reaching their fundamental limits. Clocked Storage Elements (CSEs) serve the purpose of synchronizing the logic across the entire chip and make sure that correct fun...

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Main Author:	Lakshman,Srivibhav
Other Authors:	Lau K T
Format:	Thesis-Master by Coursework
Language:	English
Published:	Nanyang Technological University 2020
Subjects:	Engineering::Electrical and electronic engineering::Electronic circuits
Online Access:	https://hdl.handle.net/10356/142930
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Institution:	Nanyang Technological University
Language:	English

id	sg-ntu-dr.10356-142930
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spelling	sg-ntu-dr.10356-1429302023-07-04T15:02:54Z Low power CMOS clocked storage elements Lakshman,Srivibhav Lau K T School of Electrical and Electronic Engineering EKTLAU@ntu.edu.sg Engineering::Electrical and electronic engineering::Electronic circuits Modern Systems-on-chips (SoCs) pack tens of millions of gates in a minuscule area which has resulted in the power consumption of chips reaching their fundamental limits. Clocked Storage Elements (CSEs) serve the purpose of synchronizing the logic across the entire chip and make sure that correct functionality is maintained. Thus, the CSEs, along with the clock are at the heart of any modern digital system. This dissertation aims to quantitatively analyze and compare between 5 different classes of flip-flops - the conventional flip-flops, TSPC-based flip-flops, differential flip-flops, pulse-triggered flip-flops and dual edge-triggered flip-flops. Performance metrics that are compared include the power-delay product (PDP), setup and hold times as well as maximum load driving capability. The power performance of the flip-flops for a variety of input patterns is also calculated. Finally, the results are presented. Master of Science (Electronics) 2020-07-14T01:43:43Z 2020-07-14T01:43:43Z 2020 Thesis-Master by Coursework https://hdl.handle.net/10356/142930 en application/pdf Nanyang Technological University
institution	Nanyang Technological University
building	NTU Library
continent	Asia
country	Singapore Singapore
content_provider	NTU Library
collection	DR-NTU
language	English
topic	Engineering::Electrical and electronic engineering::Electronic circuits
spellingShingle	Engineering::Electrical and electronic engineering::Electronic circuits Lakshman,Srivibhav Low power CMOS clocked storage elements
description	Modern Systems-on-chips (SoCs) pack tens of millions of gates in a minuscule area which has resulted in the power consumption of chips reaching their fundamental limits. Clocked Storage Elements (CSEs) serve the purpose of synchronizing the logic across the entire chip and make sure that correct functionality is maintained. Thus, the CSEs, along with the clock are at the heart of any modern digital system. This dissertation aims to quantitatively analyze and compare between 5 different classes of flip-flops - the conventional flip-flops, TSPC-based flip-flops, differential flip-flops, pulse-triggered flip-flops and dual edge-triggered flip-flops. Performance metrics that are compared include the power-delay product (PDP), setup and hold times as well as maximum load driving capability. The power performance of the flip-flops for a variety of input patterns is also calculated. Finally, the results are presented.
author2	Lau K T
author_facet	Lau K T Lakshman,Srivibhav
format	Thesis-Master by Coursework
author	Lakshman,Srivibhav
author_sort	Lakshman,Srivibhav
title	Low power CMOS clocked storage elements
title_short	Low power CMOS clocked storage elements
title_full	Low power CMOS clocked storage elements
title_fullStr	Low power CMOS clocked storage elements
title_full_unstemmed	Low power CMOS clocked storage elements
title_sort	low power cmos clocked storage elements
publisher	Nanyang Technological University
publishDate	2020
url	https://hdl.handle.net/10356/142930
_version_	1772825859887988736

Low power CMOS clocked storage elements

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