Approximate adder with reduced error

• Main Authors: Balasubramanian, Padmanabhan, Maskell, Douglas Leslie, Prasad, K.
• Other Authors: School of Computer Science and Engineering
• Format: Conference or Workshop Item
• Language: English
• Published: 2020
• Subjects: Engineering::Computer science and engineering::Hardware; Adders; Field Programmable Gate Arrays
• Online Access: https://hdl.handle.net/10356/144131
• Institution: Nanyang Technological University

A new approximate adder is proposed, which is suitable for FPGA- and ASIC-based implementations. Here, we consider an Artix-7 FPGA for the implementations using Vivado 2018.3. For 32-bit addition, the proposed approximate adder with an 8-bit least significant inaccurate sub-adder reports an improvement in the maximum frequency by 7.7% compared to the native accurate FPGA adder while consuming 22% fewer LUTs and 18.6% fewer registers. For 64-bit addition, the proposed approximate adder reports an increase in the maximum frequency by 9.1% than the accurate FPGA adder while consuming 11% fewer LUTs and 9.3% fewer registers. The power-delay product (PDP) is computed as the product of total on-chip power consumption and the minimum clock period. The proposed approximate adder achieves 14.7% and 9.3% reductions in PDP compared to the accurate FPGA adder for 32- and 64-bit additions respectively. Further, in comparison with a recent approximate adder presented in the literature, the proposed approximate adder reports a 40% reduction in the root mean square error (RMSE) while having the same design metrics.