Approximate adder with reduced error

A new approximate adder is proposed, which is suitable for FPGA- and ASIC-based implementations. Here, we consider an Artix-7 FPGA for the implementations using Vivado 2018.3. For 32-bit addition, the proposed approximate adder with an 8-bit least significant inaccurate sub-adder reports an improvem...

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Main Authors: Balasubramanian, Padmanabhan, Maskell, Douglas Leslie, Prasad, K.
Other Authors: School of Computer Science and Engineering
Format: Conference or Workshop Item
Language:English
Published: 2020
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Online Access:https://hdl.handle.net/10356/144131
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-1441312020-10-15T02:05:45Z Approximate adder with reduced error Balasubramanian, Padmanabhan Maskell, Douglas Leslie Prasad, K. School of Computer Science and Engineering 31st International Conference on Microelectronics (MIEL 2019) Centre for High Performance Embedded Systems Engineering::Computer science and engineering::Hardware Adders Field Programmable Gate Arrays A new approximate adder is proposed, which is suitable for FPGA- and ASIC-based implementations. Here, we consider an Artix-7 FPGA for the implementations using Vivado 2018.3. For 32-bit addition, the proposed approximate adder with an 8-bit least significant inaccurate sub-adder reports an improvement in the maximum frequency by 7.7% compared to the native accurate FPGA adder while consuming 22% fewer LUTs and 18.6% fewer registers. For 64-bit addition, the proposed approximate adder reports an increase in the maximum frequency by 9.1% than the accurate FPGA adder while consuming 11% fewer LUTs and 9.3% fewer registers. The power-delay product (PDP) is computed as the product of total on-chip power consumption and the minimum clock period. The proposed approximate adder achieves 14.7% and 9.3% reductions in PDP compared to the accurate FPGA adder for 32- and 64-bit additions respectively. Further, in comparison with a recent approximate adder presented in the literature, the proposed approximate adder reports a 40% reduction in the root mean square error (RMSE) while having the same design metrics. Ministry of Education (MOE) Accepted version This research is funded by the Ministry of Education (MOE), Singapore under grant MOE2018-T2-2-024. 2020-10-15T01:49:04Z 2020-10-15T01:49:04Z 2019 Conference Paper Balasubramanian, P., Maskell, D. L., & Prasad, K. (2019). Approximate adder with reduced error. 31st International Conference on Microelectronics (MIEL 2019), 293-296. doi:10.1109/MIEL.2019.8889605 978-1-7281-3419-2 https://hdl.handle.net/10356/144131 10.1109/MIEL.2019.8889605 293 296 en MOE2018-T2-2-024 © 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: https://doi.org/10.1109/MIEL.2019.8889605 application/pdf
institution Nanyang Technological University
building NTU Library
country Singapore
collection DR-NTU
language English
topic Engineering::Computer science and engineering::Hardware
Adders
Field Programmable Gate Arrays
spellingShingle Engineering::Computer science and engineering::Hardware
Adders
Field Programmable Gate Arrays
Balasubramanian, Padmanabhan
Maskell, Douglas Leslie
Prasad, K.
Approximate adder with reduced error
description A new approximate adder is proposed, which is suitable for FPGA- and ASIC-based implementations. Here, we consider an Artix-7 FPGA for the implementations using Vivado 2018.3. For 32-bit addition, the proposed approximate adder with an 8-bit least significant inaccurate sub-adder reports an improvement in the maximum frequency by 7.7% compared to the native accurate FPGA adder while consuming 22% fewer LUTs and 18.6% fewer registers. For 64-bit addition, the proposed approximate adder reports an increase in the maximum frequency by 9.1% than the accurate FPGA adder while consuming 11% fewer LUTs and 9.3% fewer registers. The power-delay product (PDP) is computed as the product of total on-chip power consumption and the minimum clock period. The proposed approximate adder achieves 14.7% and 9.3% reductions in PDP compared to the accurate FPGA adder for 32- and 64-bit additions respectively. Further, in comparison with a recent approximate adder presented in the literature, the proposed approximate adder reports a 40% reduction in the root mean square error (RMSE) while having the same design metrics.
author2 School of Computer Science and Engineering
author_facet School of Computer Science and Engineering
Balasubramanian, Padmanabhan
Maskell, Douglas Leslie
Prasad, K.
format Conference or Workshop Item
author Balasubramanian, Padmanabhan
Maskell, Douglas Leslie
Prasad, K.
author_sort Balasubramanian, Padmanabhan
title Approximate adder with reduced error
title_short Approximate adder with reduced error
title_full Approximate adder with reduced error
title_fullStr Approximate adder with reduced error
title_full_unstemmed Approximate adder with reduced error
title_sort approximate adder with reduced error
publishDate 2020
url https://hdl.handle.net/10356/144131
_version_ 1681058567599161344