Approximate adder with reduced error

• Main Authors: Balasubramanian, Padmanabhan, Maskell, Douglas Leslie, Prasad, K.
• Other Authors: School of Computer Science and Engineering
• Format: Conference or Workshop Item
• Language: English
• Published: 2020
• Subjects: Engineering::Computer science and engineering::Hardware; Adders; Field Programmable Gate Arrays
• Online Access: https://hdl.handle.net/10356/144131
• Institution: Nanyang Technological University

A new approximate adder is proposed, which is suitable for FPGA- and ASIC-based implementations. Here, we consider an Artix-7 FPGA for the implementations using Vivado 2018.3. For 32-bit addition, the proposed approximate adder with an 8-bit least significant inaccurate sub-adder reports an improvem...