Approximate adder with reduced error

A new approximate adder is proposed, which is suitable for FPGA- and ASIC-based implementations. Here, we consider an Artix-7 FPGA for the implementations using Vivado 2018.3. For 32-bit addition, the proposed approximate adder with an 8-bit least significant inaccurate sub-adder reports an improvem...

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Bibliographic Details
Main Authors: Balasubramanian, Padmanabhan, Maskell, Douglas Leslie, Prasad, K.
Other Authors: School of Computer Science and Engineering
Format: Conference or Workshop Item
Language:English
Published: 2020
Subjects:
Online Access:https://hdl.handle.net/10356/144131
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Institution: Nanyang Technological University
Language: English