Approximate adder with reduced error

• Main Authors: Balasubramanian, Padmanabhan, Maskell, Douglas Leslie, Prasad, K.
• 其他作者: School of Computer Science and Engineering
• 格式: Conference or Workshop Item
• 語言: English
• 出版: 2020
• 主題: Engineering::Computer science and engineering::Hardware; Adders; Field Programmable Gate Arrays
• 在線閱讀: https://hdl.handle.net/10356/144131
• 機構: Nanyang Technological University

A new approximate adder is proposed, which is suitable for FPGA- and ASIC-based implementations. Here, we consider an Artix-7 FPGA for the implementations using Vivado 2018.3. For 32-bit addition, the proposed approximate adder with an 8-bit least significant inaccurate sub-adder reports an improvem...