A 0.5 V 8-12 bit 300 KSPS SAR ADC with adaptive conversion time detection-and-control for high immunity to PVT variations

• Main Authors: Kim, Ju Eon, Yoo, Taegeun, Jung, Dong-Kyu, Yoon, Dong-Hyun, Seong, Kiho, Kim, Tony Tae-Hyoung, Baek, Kwang-Hyun
• 其他作者: School of Electrical and Electronic Engineering
• 格式: Article
• 語言: English
• 出版: 2021
• 主題: Engineering::Electrical and electronic engineering; Asynchronous; Compensation
• 在線閱讀: https://hdl.handle.net/10356/145808
• 機構: Nanyang Technological University

In this paper, a low power asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) involving the process, voltage, and temperature (PVT) compensation is presented. A proposed adaptive conversion time detection-and-control technique enhances the power efficiency, covering wide PVT variations. The proposed detection-and-control technique senses PVT variation in an aspect of conversion time, and adaptively controls the operation speed and power consumption. For PVT compensation, the proposed architecture includes the local supply/ground voltage. The local supply/ground voltage makes high $\vert \text{V}_{\mathrm {GS}}\vert $ for transistors in the comparator and capacitive digital-to-analog converter switches, resulting in enhanced operation speed. However, when PVT condition changes to be favorable for the conversion speed, the $\vert \text{V}_{\mathrm {GS}}\vert $ decreases for low power consumption. 30 chips were measured to verify the proposed ADC. Having the proposed architecture tested with 10 kHz input frequency, SNDR remained higher than 60 dB at unfavorable conditions such as -9 % supply voltage variation, or -20 °C temperature variation. On the other hand, at favorable conditions such as +9 % supply voltage variation, or 80 °C temperature variation, the power consumption of SAR ADC decreased without performance degradation.