A 0.5 V 8-12 bit 300 KSPS SAR ADC with adaptive conversion time detection-and-control for high immunity to PVT variations

A 0.5 V 8-12 bit 300 KSPS SAR ADC with adaptive conversion time detection-and-control for high immunity to PVT variations

In this paper, a low power asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) involving the process, voltage, and temperature (PVT) compensation is presented. A proposed adaptive conversion time detection-and-control technique enhances the power efficiency, coveri...

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Bibliographic Details
Main Authors: Kim, Ju Eon, Yoo, Taegeun, Jung, Dong-Kyu, Yoon, Dong-Hyun, Seong, Kiho, Kim, Tony Tae-Hyoung, Baek, Kwang-Hyun
Other Authors: School of Electrical and Electronic Engineering
Format: Article
Language:English
Published: 2021
Subjects:
Engineering::Electrical and electronic engineering
Asynchronous
Compensation
Online Access:https://hdl.handle.net/10356/145808
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Institution: Nanyang Technological University
Language: English

Internet

https://hdl.handle.net/10356/145808

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