A 0.5 V 8-12 bit 300 KSPS SAR ADC with adaptive conversion time detection-and-control for high immunity to PVT variations
In this paper, a low power asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) involving the process, voltage, and temperature (PVT) compensation is presented. A proposed adaptive conversion time detection-and-control technique enhances the power efficiency, coveri...
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sg-ntu-dr.10356-1458082021-01-08T08:23:50Z A 0.5 V 8-12 bit 300 KSPS SAR ADC with adaptive conversion time detection-and-control for high immunity to PVT variations Kim, Ju Eon Yoo, Taegeun Jung, Dong-Kyu Yoon, Dong-Hyun Seong, Kiho Kim, Tony Tae-Hyoung Baek, Kwang-Hyun School of Electrical and Electronic Engineering Engineering::Electrical and electronic engineering Asynchronous Compensation In this paper, a low power asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) involving the process, voltage, and temperature (PVT) compensation is presented. A proposed adaptive conversion time detection-and-control technique enhances the power efficiency, covering wide PVT variations. The proposed detection-and-control technique senses PVT variation in an aspect of conversion time, and adaptively controls the operation speed and power consumption. For PVT compensation, the proposed architecture includes the local supply/ground voltage. The local supply/ground voltage makes high $\vert \text{V}_{\mathrm {GS}}\vert $ for transistors in the comparator and capacitive digital-to-analog converter switches, resulting in enhanced operation speed. However, when PVT condition changes to be favorable for the conversion speed, the $\vert \text{V}_{\mathrm {GS}}\vert $ decreases for low power consumption. 30 chips were measured to verify the proposed ADC. Having the proposed architecture tested with 10 kHz input frequency, SNDR remained higher than 60 dB at unfavorable conditions such as -9 % supply voltage variation, or -20 °C temperature variation. On the other hand, at favorable conditions such as +9 % supply voltage variation, or 80 °C temperature variation, the power consumption of SAR ADC decreased without performance degradation. Published version 2021-01-08T08:23:49Z 2021-01-08T08:23:49Z 2020 Journal Article Kim, J. E., Yoo, T., Jung, D.-K., Yoon, D.-H., Seong, K., Kim, T. T.-K., & Baek, K.-H. (2020). A 0.5 V 8-12 bit 300 KSPS SAR ADC with adaptive conversion time detection-and-control for high immunity to PVT variations. IEEE Access, 8, 101359-101368. doi:10.1109/access.2020.2998161 2169-3536 https://hdl.handle.net/10356/145808 10.1109/ACCESS.2020.2998161 8 101359 101368 en IEEE Access © 2020 IEEE. This journal is 100% open access, which means that all content is freely available without charge to users or their institutions. All articles accepted after 12 June 2019 are published under a CC BY 4.0 license, and the author retains copyright. Users are allowed to read, download, copy, distribute, print, search, or link to the full texts of the articles, or use them for any other lawful purpose, as long as proper attribution is given. application/pdf |
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Engineering::Electrical and electronic engineering Asynchronous Compensation Kim, Ju Eon Yoo, Taegeun Jung, Dong-Kyu Yoon, Dong-Hyun Seong, Kiho Kim, Tony Tae-Hyoung Baek, Kwang-Hyun A 0.5 V 8-12 bit 300 KSPS SAR ADC with adaptive conversion time detection-and-control for high immunity to PVT variations |
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In this paper, a low power asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) involving the process, voltage, and temperature (PVT) compensation is presented. A proposed adaptive conversion time detection-and-control technique enhances the power efficiency, covering wide PVT variations. The proposed detection-and-control technique senses PVT variation in an aspect of conversion time, and adaptively controls the operation speed and power consumption. For PVT compensation, the proposed architecture includes the local supply/ground voltage. The local supply/ground voltage makes high $\vert \text{V}_{\mathrm {GS}}\vert $ for transistors in the comparator and capacitive digital-to-analog converter switches, resulting in enhanced operation speed. However, when PVT condition changes to be favorable for the conversion speed, the $\vert \text{V}_{\mathrm {GS}}\vert $ decreases for low power consumption. 30 chips were measured to verify the proposed ADC. Having the proposed architecture tested with 10 kHz input frequency, SNDR remained higher than 60 dB at unfavorable conditions such as -9 % supply voltage variation, or -20 °C temperature variation. On the other hand, at favorable conditions such as +9 % supply voltage variation, or 80 °C temperature variation, the power consumption of SAR ADC decreased without performance degradation. |
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School of Electrical and Electronic Engineering |
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School of Electrical and Electronic Engineering Kim, Ju Eon Yoo, Taegeun Jung, Dong-Kyu Yoon, Dong-Hyun Seong, Kiho Kim, Tony Tae-Hyoung Baek, Kwang-Hyun |
format |
Article |
author |
Kim, Ju Eon Yoo, Taegeun Jung, Dong-Kyu Yoon, Dong-Hyun Seong, Kiho Kim, Tony Tae-Hyoung Baek, Kwang-Hyun |
author_sort |
Kim, Ju Eon |
title |
A 0.5 V 8-12 bit 300 KSPS SAR ADC with adaptive conversion time detection-and-control for high immunity to PVT variations |
title_short |
A 0.5 V 8-12 bit 300 KSPS SAR ADC with adaptive conversion time detection-and-control for high immunity to PVT variations |
title_full |
A 0.5 V 8-12 bit 300 KSPS SAR ADC with adaptive conversion time detection-and-control for high immunity to PVT variations |
title_fullStr |
A 0.5 V 8-12 bit 300 KSPS SAR ADC with adaptive conversion time detection-and-control for high immunity to PVT variations |
title_full_unstemmed |
A 0.5 V 8-12 bit 300 KSPS SAR ADC with adaptive conversion time detection-and-control for high immunity to PVT variations |
title_sort |
0.5 v 8-12 bit 300 ksps sar adc with adaptive conversion time detection-and-control for high immunity to pvt variations |
publishDate |
2021 |
url |
https://hdl.handle.net/10356/145808 |
_version_ |
1690658314604511232 |