Thermal simulations of 3D through silicon via-based ion traps

• Main Author: Bi, Xinwen
• Other Authors: Tan Chuan Seng
• Format: Thesis-Master by Coursework
• Language: English
• Published: Nanyang Technological University 2022
• Subjects: Engineering::Electrical and electronic engineering::Electronic packaging
• Online Access: https://hdl.handle.net/10356/155524
• Institution: Nanyang Technological University

This work presents possible solutions to mitigate the temperature increase concern in through silicon via (TSV) integrated ion traps using two approaches: (1) heat generation reduction and (2) heat dissipation enhancement. A power loss and temperature increase associated with the ion trap is carefully studied by investigating the electrical conductivity of silicon, the grounding plane, the number of TSVs, and the pitch of the TSVs. In our experiments, we found that a silicon substrate can be used, or a ground plane can be integrated below the electrodes to maintain the temperature below 2 K. Compared to the number of TSVs density, the effect of the pitch is less noticeable. Additionally, a thermal dissipation medium has been added between the ion trap and the interposer to provide highly efficient heat dissipation path. Similarly, in order to select an appropriate interposer substrate, the thermal conductivity of the interposer substrate is evaluated in relation to temperature increase. Ion trap implementation at a large scale can be achieved by understanding the dissipation constraints and designing efficient thermal management methods.