High-performance CMOS digital multiplier IC design
A digital multiplier is a common block in processors, and its speed has a significant impact on the performance of the chip. Many new design ideas have emerged around how to improve the speed of multipliers, including pipeline structure, Wallace Tree structure, and Booth encoding. The Wallace Tree s...
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| 格式: | Thesis-Master by Coursework |
| 語言: | English |
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Nanyang Technological University
2023
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| 在線閱讀: | https://hdl.handle.net/10356/164473 |
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| 機構: | Nanyang Technological University |
| 語言: | English |