Implementation of industry-standard functional coverage in UVM testbench for SoC level verification
As ICs（Integrated Circuits）process technologies and SoC (system-on-chip) design techniques continue to advance, IC chip designs continue to grow in size and complexity. Verification IP automates the generation of test stimulus, data comparison and coverage statistics, and its verification components...
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| 格式: | Thesis-Master by Coursework |
| 語言: | English |
| 出版: |
Nanyang Technological University
2023
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| 主題: | |
| 在線閱讀: | https://hdl.handle.net/10356/166397 |
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