A functional failure detection method for semiconductor design safety verification
As the function of SoC becomes more and more powerful, its design complexity is also increasing, the overall circuit complexity will inevitably increase safety risks. Therefore, for the verification work of SoC, functional safety verification has been receiving greater attention. Efficient and compl...
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| Format: | Thesis-Master by Coursework |
| Language: | English |
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Nanyang Technological University
2023
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| Online Access: | https://hdl.handle.net/10356/166551 |
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| Institution: | Nanyang Technological University |
| Language: | English |
| Summary: | As the function of SoC becomes more and more powerful, its design complexity is also increasing, the overall circuit complexity will inevitably increase safety risks. Therefore, for the verification work of SoC, functional safety verification has been receiving greater attention. Efficient and complete functional safety verification plays an important role in ensuring a reliable and safe operation of the whole circuit. This dissertation will be based on the author's internship experience in Infineon Technologies Asia Pacific Pte Ltd. The first part takes the functional safety verification of SoC as the starting point. Firstly, it introduces the development history of SoC chips, the characteristics of SoC verification, the basic requirements of functional safety verification, and the basic tools used in verification work. The second part takes designing and verifying a memory as the starting point to introduce the learning and application of basic tools; The third part, taking specific MCU products as the working environment, introduces the specific safety monitor design and verification process; The fourth part summarizes the experimental results and reviews the harvest plus perception of the internship experience. |
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