A functional failure detection method for semiconductor design safety verification

As the function of SoC becomes more and more powerful, its design complexity is also increasing, the overall circuit complexity will inevitably increase safety risks. Therefore, for the verification work of SoC, functional safety verification has been receiving greater attention. Efficient and compl...

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Main Author: Hai, Zhuoran
Other Authors: Meng-Hiot Lim
Format: Thesis-Master by Coursework
Language:English
Published: Nanyang Technological University 2023
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Online Access:https://hdl.handle.net/10356/166551
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-1665512023-07-04T15:28:53Z A functional failure detection method for semiconductor design safety verification Hai, Zhuoran Meng-Hiot Lim School of Electrical and Electronic Engineering Technical University of Munich EMHLIM@ntu.edu.sg Engineering::Electrical and electronic engineering::Integrated circuits As the function of SoC becomes more and more powerful, its design complexity is also increasing, the overall circuit complexity will inevitably increase safety risks. Therefore, for the verification work of SoC, functional safety verification has been receiving greater attention. Efficient and complete functional safety verification plays an important role in ensuring a reliable and safe operation of the whole circuit. This dissertation will be based on the author's internship experience in Infineon Technologies Asia Pacific Pte Ltd. The first part takes the functional safety verification of SoC as the starting point. Firstly, it introduces the development history of SoC chips, the characteristics of SoC verification, the basic requirements of functional safety verification, and the basic tools used in verification work. The second part takes designing and verifying a memory as the starting point to introduce the learning and application of basic tools; The third part, taking specific MCU products as the working environment, introduces the specific safety monitor design and verification process; The fourth part summarizes the experimental results and reviews the harvest plus perception of the internship experience. Master of Science (Integrated Circuit Design) 2023-05-03T02:57:45Z 2023-05-03T02:57:45Z 2023 Thesis-Master by Coursework Hai, Z. (2023). A functional failure detection method for semiconductor design safety verification. Master's thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/166551 https://hdl.handle.net/10356/166551 en application/pdf Nanyang Technological University
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic Engineering::Electrical and electronic engineering::Integrated circuits
spellingShingle Engineering::Electrical and electronic engineering::Integrated circuits
Hai, Zhuoran
A functional failure detection method for semiconductor design safety verification
description As the function of SoC becomes more and more powerful, its design complexity is also increasing, the overall circuit complexity will inevitably increase safety risks. Therefore, for the verification work of SoC, functional safety verification has been receiving greater attention. Efficient and complete functional safety verification plays an important role in ensuring a reliable and safe operation of the whole circuit. This dissertation will be based on the author's internship experience in Infineon Technologies Asia Pacific Pte Ltd. The first part takes the functional safety verification of SoC as the starting point. Firstly, it introduces the development history of SoC chips, the characteristics of SoC verification, the basic requirements of functional safety verification, and the basic tools used in verification work. The second part takes designing and verifying a memory as the starting point to introduce the learning and application of basic tools; The third part, taking specific MCU products as the working environment, introduces the specific safety monitor design and verification process; The fourth part summarizes the experimental results and reviews the harvest plus perception of the internship experience.
author2 Meng-Hiot Lim
author_facet Meng-Hiot Lim
Hai, Zhuoran
format Thesis-Master by Coursework
author Hai, Zhuoran
author_sort Hai, Zhuoran
title A functional failure detection method for semiconductor design safety verification
title_short A functional failure detection method for semiconductor design safety verification
title_full A functional failure detection method for semiconductor design safety verification
title_fullStr A functional failure detection method for semiconductor design safety verification
title_full_unstemmed A functional failure detection method for semiconductor design safety verification
title_sort functional failure detection method for semiconductor design safety verification
publisher Nanyang Technological University
publishDate 2023
url https://hdl.handle.net/10356/166551
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