Decapsulation of IC packages with silver wire bonds for failure analysis

• Main Author: Matthews, Lynzen
• Other Authors: Gan Chee Lip
• Format: Final Year Project
• Language: English
• Published: Nanyang Technological University 2023
• Subjects: Engineering::Materials
• Online Access: https://hdl.handle.net/10356/166877
• Institution: Nanyang Technological University

Failure analysis in Integrated Circuits (IC) packages has always played a vital role in supporting manufacturing modules in the semiconductor industry. Failure analysis can provide essential information on product failure modes that ensure the employment of accurate corrective actions to improve quality and reliability of IC chips. This stimulates technological advancements via efforts for failure prevention and modifications in the design and manufacturing of IC chips to create systems that are more resilient against future product failures. In their final packaged form, IC packages conceal many possible failure modes that could occur in the inner components. This limits failure analysis methods which can only provide a broad idea of failure through electrical testing, visible inspection of the package, and non-destructive testing using computed tomography x-ray imaging or scanning acoustic microscopy. To perform a holistic examinations of failed chips via optical microscopy or SEM-EDX (Scanning Electron Microscope-Energy Dispersive X-ray Spectroscopy) for elemental analysis, decapsulation of the epoxy molding compound has to be carried out to expose the inner components such as the wirebonds or the chip itself. This Final Year Project aims to create a basic recipe that optimizes the decapsulation of a small sized STM32 IC chip with Ag wirebonds. First, a Ytterbium Fibre LASER pre-decapsulator with extremely high etch rate acted as a bulk epoxy remover. Next, a Microwave-Induced Plasma (MIP) method is utilized as a moderate etch rate, highly selective decapsulator to expose the inner components of the IC package. The main focus of this project would be to augment the MIP process to preserve specifically the Ag wirebonds and metal leadframes of STM32 microcontroller samples while not causing any damage to the Si die, bond pads and stitch bonds on the leadframes. This was done by incorporating a H2/Ar gas recipe for MIP and optimizing machine parameters to produce a well-decapsulated sample, verified by optical microscope images or SEM images. Furthermore, binary data will be programmed into the sample chips and a post-decapsulation data readout would be done to validate the preservation of the data retention capabilities and electrical connectivity of our samples.