ASIC implementation of a high speed and low power scalar product computation unit

• Main Author: Low, Jeremy Yung Shern.
• Other Authors: Chan Pak Kwong
• Format: Final Year Project
• Language: English
• Published: 2009
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: http://hdl.handle.net/10356/16733
• Institution: Nanyang Technological University

This project involves the design, synthesis and placement & routing of improved 16-bit 15-element unsigned inner product architecture. Improvement to the design were made in the carry free addition stage, which is also known as column compression stage or reduction stage, whereby counters are in...