ASIC implementation of a high speed and low power scalar product computation unit

• 主要作者: Low, Jeremy Yung Shern.
• 其他作者: Chan Pak Kwong
• 格式: Final Year Project
• 語言: English
• 出版: 2009
• 主題: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• 在線閱讀: http://hdl.handle.net/10356/16733
• 機構: Nanyang Technological University

This project involves the design, synthesis and placement & routing of improved 16-bit 15-element unsigned inner product architecture. Improvement to the design were made in the carry free addition stage, which is also known as column compression stage or reduction stage, whereby counters are in...