Low power CMOS multiplier IC design
This dissertation mainly studies the design of a 16-bit low-power multiplier. Based on the widespread application of multipliers and the market's demand for low-power circuits, the main goal of this dissertation is to reduce the power consumption of the multiplier by no less than one-tenth. The...
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| 格式: | Thesis-Master by Coursework |
| 語言: | English |
| 出版: |
Nanyang Technological University
2023
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| 主題: | |
| 在線閱讀: | https://hdl.handle.net/10356/167760 |
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| 機構: | Nanyang Technological University |
| 語言: | English |
| 總結: | This dissertation mainly studies the design of a 16-bit low-power multiplier. Based on the widespread application of multipliers and the market's demand for low-power circuits, the main goal of this dissertation is to reduce the power consumption of the multiplier by no less than one-tenth. The design of low-power multipliers will be carried out through two ways: improving the structure of the multiplier and the clock cycle. Verilog will be used to design the multiplier in this dissertation, and the code will be compiled using Synopsys VCS. Code simulation will be conducted using Synopsys Design Vision, and power consumption of the circuit will be measured. A 65nm library will be used for simulation. |
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