Low power CMOS multiplier IC design

Low power CMOS multiplier IC design

This dissertation mainly studies the design of a 16-bit low-power multiplier. Based on the widespread application of multipliers and the market's demand for low-power circuits, the main goal of this dissertation is to reduce the power consumption of the multiplier by no less than one-tenth. The...

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主要作者: Zhang, Wanqing
其他作者: Gwee Bah Hwee
格式: Thesis-Master by Coursework
語言:English
出版: Nanyang Technological University 2023
主題:
Engineering::Electrical and electronic engineering
在線閱讀:https://hdl.handle.net/10356/167760
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機構: Nanyang Technological University
語言: English
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spelling sg-ntu-dr.10356-1677602023-07-04T16:47:26Z Low power CMOS multiplier IC design Zhang, Wanqing Gwee Bah Hwee School of Electrical and Electronic Engineering ebhgwee@ntu.edu.sg Engineering::Electrical and electronic engineering This dissertation mainly studies the design of a 16-bit low-power multiplier. Based on the widespread application of multipliers and the market's demand for low-power circuits, the main goal of this dissertation is to reduce the power consumption of the multiplier by no less than one-tenth. The design of low-power multipliers will be carried out through two ways: improving the structure of the multiplier and the clock cycle. Verilog will be used to design the multiplier in this dissertation, and the code will be compiled using Synopsys VCS. Code simulation will be conducted using Synopsys Design Vision, and power consumption of the circuit will be measured. A 65nm library will be used for simulation. Master of Science (Electronics) 2023-05-18T05:38:41Z 2023-05-18T05:38:41Z 2023 Thesis-Master by Coursework Zhang, W. (2023). Low power CMOS multiplier IC design. Master's thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/167760 https://hdl.handle.net/10356/167760 en application/pdf Nanyang Technological University
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic Engineering::Electrical and electronic engineering
spellingShingle Engineering::Electrical and electronic engineering
Zhang, Wanqing
Low power CMOS multiplier IC design
description This dissertation mainly studies the design of a 16-bit low-power multiplier. Based on the widespread application of multipliers and the market's demand for low-power circuits, the main goal of this dissertation is to reduce the power consumption of the multiplier by no less than one-tenth. The design of low-power multipliers will be carried out through two ways: improving the structure of the multiplier and the clock cycle. Verilog will be used to design the multiplier in this dissertation, and the code will be compiled using Synopsys VCS. Code simulation will be conducted using Synopsys Design Vision, and power consumption of the circuit will be measured. A 65nm library will be used for simulation.
author2 Gwee Bah Hwee
author_facet Gwee Bah Hwee
Zhang, Wanqing
format Thesis-Master by Coursework
author Zhang, Wanqing
author_sort Zhang, Wanqing
title Low power CMOS multiplier IC design
title_short Low power CMOS multiplier IC design
title_full Low power CMOS multiplier IC design
title_fullStr Low power CMOS multiplier IC design
title_full_unstemmed Low power CMOS multiplier IC design
title_sort low power cmos multiplier ic design
publisher Nanyang Technological University
publishDate 2023
url https://hdl.handle.net/10356/167760
_version_ 1772828610121433088

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