Low power CMOS multiplier IC design
This dissertation mainly studies the design of a 16-bit low-power multiplier. Based on the widespread application of multipliers and the market's demand for low-power circuits, the main goal of this dissertation is to reduce the power consumption of the multiplier by no less than one-tenth. The...
Saved in:
| 主要作者: | |
|---|---|
| 其他作者: | |
| 格式: | Thesis-Master by Coursework |
| 語言: | English |
| 出版: |
Nanyang Technological University
2023
|
| 主題: | |
| 在線閱讀: | https://hdl.handle.net/10356/167760 |
| 標簽: |
添加標簽
沒有標簽, 成為第一個標記此記錄!
|
| 機構: | Nanyang Technological University |
| 語言: | English |