Design of an ultra-low-voltage CMOS relaxation clock oscillator

• Main Author: Zhao, Bingbing
• Other Authors: Chan Pak Kwong
• Format: Thesis-Master by Coursework
• Language: English
• Published: Nanyang Technological University 2023
• Subjects: Engineering::Electrical and electronic engineering::Electronic circuits
• Online Access: https://hdl.handle.net/10356/168607
• Institution: Nanyang Technological University

This dissertation presents the design of a 0.45 V fully-integrated relaxation oscillator using TSMC 40nm CMOS process technology. It comprises, a 2-Transistor (2-T) voltage reference, a current reference generator and a comparator in conjunction of the associated switched-capacitor network. The 2-T voltage reference generates an output voltage of 202 mV and displays the low temperature coefficient. The current reference generator consists of an ultra-low voltage amplifier having an embedded current mirror and a reference composite resistor under a feedback loop and multiple open-loop current mirrors for copying reference currents to generate Proportional-to-Absolute-Temperature (PTAT) de ay. This aims to compensate the delay of comparator with Complementary-to-Absolute-Temperature (CTAT) characteristic. The oscillator action is achieved by the reference current as the capacitor charging current and the switched network which is controlled by the operation of comparator to reset the capacitors. The simulation results have shown that at typical corner and room temperature, the output frequency is 112.87 kHz at 0.45V supply and the temperature coefficient (T.C.) is 46.1 ppm/°C. This yields 0.36% frequency deviation. For 200 runs of Monte-Carlo simulation, the obtained average T.C. is 137 ppm/°C and the standard deviation is 85.28 ppm/°C, leading to the process sensitivity of 7.12%. Compared to the prior-art works, the performance metrics are good in view of very low supply operation.