Transposable 9T-SRAM computation-in-memory for on-chip learning with probability-based single-slope SAR hybrid ADC for edge devices

Transposable 9T-SRAM computation-in-memory for on-chip learning with probability-based single-slope SAR hybrid ADC for edge devices

This letter proposes a two-way transposable SRAM computation-in-memory (CIM) macro for inference and training in convolutional neural networks (CNNs). A novel 9T SRAM bit-cell conducts local two-way computing without shared processing units, achieving higher-processing throughput from every bit-cell...

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Main Authors: Jo, Yong-Jun, Zhang, Xin, Liu, Jiahao, Zhou, Jun, Zheng, Yuanjin, Kim, Tony Tae-Hyoung
其他作者: School of Electrical and Electronic Engineering
格式: Article
語言:English
出版: 2023
主題:
Engineering::Electrical and electronic engineering
On-Chip Learning
Zero-Skip
在線閱讀:https://hdl.handle.net/10356/170098
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總結:This letter proposes a two-way transposable SRAM computation-in-memory (CIM) macro for inference and training in convolutional neural networks (CNNs). A novel 9T SRAM bit-cell conducts local two-way computing without shared processing units, achieving higher-processing throughput from every bit-cell operating in one CIM cycle. This letter also proposes a probability-based single-slope (SS) and successive approximation (SAR) hybrid analog-to-digital converter (ADC) for energy efficiency improvement by utilizing the probability density function of multiply and accumulation (MAC). The proposed ADC also supports the ReLU-based zero skip function without additional circuitry. The prototype was fabricated in 180-nm CMOS technology and achieved an energy efficiency of 6.61 (1.65) TOPS/W for inference (training).

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