Transposable 9T-SRAM computation-in-memory for on-chip learning with probability-based single-slope SAR hybrid ADC for edge devices

• Main Authors: Jo, Yong-Jun, Zhang, Xin, Liu, Jiahao, Zhou, Jun, Zheng, Yuanjin, Kim, Tony Tae-Hyoung
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2023
• Subjects: Engineering::Electrical and electronic engineering; On-Chip Learning; Zero-Skip
• Online Access: https://hdl.handle.net/10356/170098
• Institution: Nanyang Technological University

This letter proposes a two-way transposable SRAM computation-in-memory (CIM) macro for inference and training in convolutional neural networks (CNNs). A novel 9T SRAM bit-cell conducts local two-way computing without shared processing units, achieving higher-processing throughput from every bit-cell operating in one CIM cycle. This letter also proposes a probability-based single-slope (SS) and successive approximation (SAR) hybrid analog-to-digital converter (ADC) for energy efficiency improvement by utilizing the probability density function of multiply and accumulation (MAC). The proposed ADC also supports the ReLU-based zero skip function without additional circuitry. The prototype was fabricated in 180-nm CMOS technology and achieved an energy efficiency of 6.61 (1.65) TOPS/W for inference (training).