CMOS-fabricated ring surface ion trap with TSV integration

We present the design, fabrication, and test of ring surface trap on 12-inch wafers with a CMOS process. The design is based on Through Silicon Vias (TSV) interconnects. Up to 200 ions were loaded and cooled; preliminary compensations of electrostatic potential imperfections show that rotational sym...

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Main Authors: Zhao, Peng, Lim, Yu Dian, Li, Hong Yu, Likforman, Jean-Pierre, Guidoni, Luca, Desormeaux, Lilay Gros, Tan, Chuan Seng
Other Authors: School of Electrical and Electronic Engineering
Format: Conference or Workshop Item
Language:English
Published: 2024
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Online Access:https://hdl.handle.net/10356/175533
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-1755332024-05-03T15:40:49Z CMOS-fabricated ring surface ion trap with TSV integration Zhao, Peng Lim, Yu Dian Li, Hong Yu Likforman, Jean-Pierre Guidoni, Luca Desormeaux, Lilay Gros Tan, Chuan Seng School of Electrical and Electronic Engineering 2023 International Electron Devices Meeting (IEDM) Institute of Microelectronics, A*STAR Engineering Fabrication Electron traps We present the design, fabrication, and test of ring surface trap on 12-inch wafers with a CMOS process. The design is based on Through Silicon Vias (TSV) interconnects. Up to 200 ions were loaded and cooled; preliminary compensations of electrostatic potential imperfections show that rotational symmetry can be partially restored. National Research Foundation (NRF) Submitted/Accepted version This research was co-supported by ANR-NRF Joint Grant Call NRF2020-NRF-ANR073 HIT. We acknowledge the fabrication support from IME and AMF, Singapore. 2024-04-30T06:12:09Z 2024-04-30T06:12:09Z 2023 Conference Paper Zhao, P., Lim, Y. D., Li, H. Y., Likforman, J., Guidoni, L., Desormeaux, L. G. & Tan, C. S. (2023). CMOS-fabricated ring surface ion trap with TSV integration. 2023 International Electron Devices Meeting (IEDM). https://dx.doi.org/10.1109/IEDM45741.2023.10413875 9798350327670 2156-017X https://hdl.handle.net/10356/175533 10.1109/IEDM45741.2023.10413875 2-s2.0-85185606737 en NRF2020-NRF-ANR073 HIT © 2023 IEEE. All rights reserved. This article may be downloaded for personal use only. Any other use requires prior permission of the copyright holder. The Version of Record is available online at http://doi.org/10.1109/IEDM45741.2023.10413875. application/pdf
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic Engineering
Fabrication
Electron traps
spellingShingle Engineering
Fabrication
Electron traps
Zhao, Peng
Lim, Yu Dian
Li, Hong Yu
Likforman, Jean-Pierre
Guidoni, Luca
Desormeaux, Lilay Gros
Tan, Chuan Seng
CMOS-fabricated ring surface ion trap with TSV integration
description We present the design, fabrication, and test of ring surface trap on 12-inch wafers with a CMOS process. The design is based on Through Silicon Vias (TSV) interconnects. Up to 200 ions were loaded and cooled; preliminary compensations of electrostatic potential imperfections show that rotational symmetry can be partially restored.
author2 School of Electrical and Electronic Engineering
author_facet School of Electrical and Electronic Engineering
Zhao, Peng
Lim, Yu Dian
Li, Hong Yu
Likforman, Jean-Pierre
Guidoni, Luca
Desormeaux, Lilay Gros
Tan, Chuan Seng
format Conference or Workshop Item
author Zhao, Peng
Lim, Yu Dian
Li, Hong Yu
Likforman, Jean-Pierre
Guidoni, Luca
Desormeaux, Lilay Gros
Tan, Chuan Seng
author_sort Zhao, Peng
title CMOS-fabricated ring surface ion trap with TSV integration
title_short CMOS-fabricated ring surface ion trap with TSV integration
title_full CMOS-fabricated ring surface ion trap with TSV integration
title_fullStr CMOS-fabricated ring surface ion trap with TSV integration
title_full_unstemmed CMOS-fabricated ring surface ion trap with TSV integration
title_sort cmos-fabricated ring surface ion trap with tsv integration
publishDate 2024
url https://hdl.handle.net/10356/175533
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