CMOS-fabricated ring surface ion trap with TSV integration

CMOS-fabricated ring surface ion trap with TSV integration

We present the design, fabrication, and test of ring surface trap on 12-inch wafers with a CMOS process. The design is based on Through Silicon Vias (TSV) interconnects. Up to 200 ions were loaded and cooled; preliminary compensations of electrostatic potential imperfections show that rotational sym...

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書目詳細資料
Main Authors:	Zhao, Peng, Lim, Yu Dian, Li, Hong Yu, Likforman, Jean-Pierre, Guidoni, Luca, Desormeaux, Lilay Gros, Tan, Chuan Seng
其他作者:	School of Electrical and Electronic Engineering
格式:	Conference or Workshop Item
語言:	English
出版:	2024
主題:	Engineering Fabrication Electron traps
在線閱讀:	https://hdl.handle.net/10356/175533
標簽:	添加標簽沒有標簽, 成為第一個標記此記錄!

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