Effects of vacancies on device performance
A process to fabricate sub-nanometer MOS transistor, is being demonstrated through an ion implantation step by the TSUPREM4 process simulator and MEDICI device simulator. The main objective of this report is to investigate the effects of the vacancies on device performance. Crystalline (100) silicon...
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| 主要作者: | |
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| 格式: | Final Year Project |
| 語言: | English |
| 出版: |
2009
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| 主題: | |
| 在線閱讀: | http://hdl.handle.net/10356/17983 |
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| 機構: | Nanyang Technological University |
| 語言: | English |
| 總結: | A process to fabricate sub-nanometer MOS transistor, is being demonstrated through an ion implantation step by the TSUPREM4 process simulator and MEDICI device simulator. The main objective of this report is to investigate the effects of the vacancies on device performance. Crystalline (100) silicon wafers of n-type with concentration of 10^16 cm^-3 uniformly distributed are used throughout the simulation. High concentrations of vacancies are introduced into the silicon substrate by BF2 implantation. The positions where the vacancies are being located within the silicon substrate can be controlled by modulating the implant energies. With the vacancies incorporated into the silicon substrate, it reduces the junction depth (Xj) after the post activation annealing. It is significant to mention that the fabrication steps involved in the simulations slightly differs from the main fabrication process steps in the industry. |
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