Effects of vacancies on device performance

A process to fabricate sub-nanometer MOS transistor, is being demonstrated through an ion implantation step by the TSUPREM4 process simulator and MEDICI device simulator. The main objective of this report is to investigate the effects of the vacancies on device performance. Crystalline (100) silicon...

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Main Author: Yan, Alan Yik Loon
Other Authors: Pey Kin Leong
Format: Final Year Project
Language:English
Published: 2009
Subjects:
Online Access:http://hdl.handle.net/10356/17983
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-179832023-07-07T15:44:12Z Effects of vacancies on device performance Yan, Alan Yik Loon Pey Kin Leong School of Electrical and Electronic Engineering DRNTU::Engineering A process to fabricate sub-nanometer MOS transistor, is being demonstrated through an ion implantation step by the TSUPREM4 process simulator and MEDICI device simulator. The main objective of this report is to investigate the effects of the vacancies on device performance. Crystalline (100) silicon wafers of n-type with concentration of 10^16 cm^-3 uniformly distributed are used throughout the simulation. High concentrations of vacancies are introduced into the silicon substrate by BF2 implantation. The positions where the vacancies are being located within the silicon substrate can be controlled by modulating the implant energies. With the vacancies incorporated into the silicon substrate, it reduces the junction depth (Xj) after the post activation annealing. It is significant to mention that the fabrication steps involved in the simulations slightly differs from the main fabrication process steps in the industry. Bachelor of Engineering 2009-06-18T06:50:58Z 2009-06-18T06:50:58Z 2009 2009 Final Year Project (FYP) http://hdl.handle.net/10356/17983 en Nanyang Technological University 79 p. application/pdf
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic DRNTU::Engineering
spellingShingle DRNTU::Engineering
Yan, Alan Yik Loon
Effects of vacancies on device performance
description A process to fabricate sub-nanometer MOS transistor, is being demonstrated through an ion implantation step by the TSUPREM4 process simulator and MEDICI device simulator. The main objective of this report is to investigate the effects of the vacancies on device performance. Crystalline (100) silicon wafers of n-type with concentration of 10^16 cm^-3 uniformly distributed are used throughout the simulation. High concentrations of vacancies are introduced into the silicon substrate by BF2 implantation. The positions where the vacancies are being located within the silicon substrate can be controlled by modulating the implant energies. With the vacancies incorporated into the silicon substrate, it reduces the junction depth (Xj) after the post activation annealing. It is significant to mention that the fabrication steps involved in the simulations slightly differs from the main fabrication process steps in the industry.
author2 Pey Kin Leong
author_facet Pey Kin Leong
Yan, Alan Yik Loon
format Final Year Project
author Yan, Alan Yik Loon
author_sort Yan, Alan Yik Loon
title Effects of vacancies on device performance
title_short Effects of vacancies on device performance
title_full Effects of vacancies on device performance
title_fullStr Effects of vacancies on device performance
title_full_unstemmed Effects of vacancies on device performance
title_sort effects of vacancies on device performance
publishDate 2009
url http://hdl.handle.net/10356/17983
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