Ag/Ti/GeS/Ag bidirectional conductive-bridge selector with low turn-off latency, high endurance, and enhanced switching uniformity

• Main Authors: Ali, Asif, Abbas, Haider, Li, Jiayi, Jung, Jongwan, Ang, Diing Shenp
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2025
• Subjects: Engineering; Bidirectional threshold switching; Chalcogenide switching material
• Online Access: https://hdl.handle.net/10356/182203
• Institution: Nanyang Technological University

To fulfill the demands of three-dimensional (3D) cross-point array architectures in embedded memories, selectors with low voltage and low off current with high selectivity are imperative. Selector devices with reliable pulsed switching performance at a logic-compatible voltage are crucial for achieving the ultimate goal of embedded 3D universal cross-point memory. While resistive ReRAM systems offer high density and ultralow power consumption, the 3D cross-point array introduces challenges such as sneak path currents during read and write operations. To overcome these problems, the selectors must be integrated into each cross-point cell. Although selector devices have been extensively studied, no singular material system has currently fulfilled all the vital needs for integration with nonvolatile memory. Here, we demonstrate an Ag-gated GeS-based bidirectional threshold switching selector device (Ag/Ti/GeS/Ag) with a highly uniform cycle-to-cycle and device-to-device switching performance. The device demonstrates highly uniform bidirectional threshold switching with promising attributes, including low threshold voltages (∼±0.22 V), low off current (∼pA), large selectivity window (∼3 × 108), an endurance of more than 109 cycles, and an on/off switching latency of 50 ns at 1 V pulsed operations. The simple material configuration of the selector device (Ag/Ti/GeS/Ag) facilitates easy fabrication, and its uniform switching performance makes it suitable for 3D cross-point integration with nonvolatile memory cells in a one-selector-one-resistor array configuration.