Scalable compact modeling for nanometer CMOS technology

This thesis documents the compact model developed for bulk MOSFET and double-gate MOSFET. The unified regional modeling approach is used in the physics-based scalable model development for bulk and double-gate MOSFETs. Surface potential models are developed regionally in accumulation, weak accumulat...

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Bibliographic Details
Main Author: See, Guan Huei
Other Authors: Zhou Xing
Format: Theses and Dissertations
Language:English
Published: 2009
Subjects:
Online Access:https://hdl.handle.net/10356/18733
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Institution: Nanyang Technological University
Language: English
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Summary:This thesis documents the compact model developed for bulk MOSFET and double-gate MOSFET. The unified regional modeling approach is used in the physics-based scalable model development for bulk and double-gate MOSFETs. Surface potential models are developed regionally in accumulation, weak accumulation, depletion, volume and strong inversion regions, which are subsequently combined using interpolation functions to ensure smooth higher order derivatives. New unified regional-based short-channel effects are developed to improve the physical scalability of the charge model. A new concept that defines two separate saturation voltages at source and drain, referenced to bulk (or ground for double-gate), respectively, is introduced to meet the Gummel symmetry requirement and to allow possible extension to asymmetric source/drain devices within the same core model. A novel approach to unifying compact models for different non-classical MOS structures, such as ultra-thin body SOI and symmetric/asymmetric double-gate MOSFETs, is proposed. Explicit surface and zero-field potentials for common-gate asymmetric double-gate MOSFETs are solved regionally and the unified solutions are applied in the explicit drain-current model for double-gate MOSFETs. Explicit surface potentials for double-gate MOSFET with quantum mechanical correction are also developed. The research demonstrates a closer step towards the unification of MOS models for future generation non-classical MOS devices.