Scalable compact modeling for nanometer CMOS technology

This thesis documents the compact model developed for bulk MOSFET and double-gate MOSFET. The unified regional modeling approach is used in the physics-based scalable model development for bulk and double-gate MOSFETs. Surface potential models are developed regionally in accumulation, weak accumulat...

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Main Author: See, Guan Huei
Other Authors: Zhou Xing
Format: Theses and Dissertations
Language:English
Published: 2009
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Online Access:https://hdl.handle.net/10356/18733
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-187332023-07-04T17:02:41Z Scalable compact modeling for nanometer CMOS technology See, Guan Huei Zhou Xing School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Semiconductors This thesis documents the compact model developed for bulk MOSFET and double-gate MOSFET. The unified regional modeling approach is used in the physics-based scalable model development for bulk and double-gate MOSFETs. Surface potential models are developed regionally in accumulation, weak accumulation, depletion, volume and strong inversion regions, which are subsequently combined using interpolation functions to ensure smooth higher order derivatives. New unified regional-based short-channel effects are developed to improve the physical scalability of the charge model. A new concept that defines two separate saturation voltages at source and drain, referenced to bulk (or ground for double-gate), respectively, is introduced to meet the Gummel symmetry requirement and to allow possible extension to asymmetric source/drain devices within the same core model. A novel approach to unifying compact models for different non-classical MOS structures, such as ultra-thin body SOI and symmetric/asymmetric double-gate MOSFETs, is proposed. Explicit surface and zero-field potentials for common-gate asymmetric double-gate MOSFETs are solved regionally and the unified solutions are applied in the explicit drain-current model for double-gate MOSFETs. Explicit surface potentials for double-gate MOSFET with quantum mechanical correction are also developed. The research demonstrates a closer step towards the unification of MOS models for future generation non-classical MOS devices. DOCTOR OF PHILOSOPHY (EEE) 2009-07-07T03:54:59Z 2009-07-07T03:54:59Z 2009 2009 Thesis See, G. H. (2009). Scalable compact modeling for nanometer CMOS technology. Doctoral thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/18733 10.32657/10356/18733 en 229 p. application/pdf
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic DRNTU::Engineering::Electrical and electronic engineering::Semiconductors
spellingShingle DRNTU::Engineering::Electrical and electronic engineering::Semiconductors
See, Guan Huei
Scalable compact modeling for nanometer CMOS technology
description This thesis documents the compact model developed for bulk MOSFET and double-gate MOSFET. The unified regional modeling approach is used in the physics-based scalable model development for bulk and double-gate MOSFETs. Surface potential models are developed regionally in accumulation, weak accumulation, depletion, volume and strong inversion regions, which are subsequently combined using interpolation functions to ensure smooth higher order derivatives. New unified regional-based short-channel effects are developed to improve the physical scalability of the charge model. A new concept that defines two separate saturation voltages at source and drain, referenced to bulk (or ground for double-gate), respectively, is introduced to meet the Gummel symmetry requirement and to allow possible extension to asymmetric source/drain devices within the same core model. A novel approach to unifying compact models for different non-classical MOS structures, such as ultra-thin body SOI and symmetric/asymmetric double-gate MOSFETs, is proposed. Explicit surface and zero-field potentials for common-gate asymmetric double-gate MOSFETs are solved regionally and the unified solutions are applied in the explicit drain-current model for double-gate MOSFETs. Explicit surface potentials for double-gate MOSFET with quantum mechanical correction are also developed. The research demonstrates a closer step towards the unification of MOS models for future generation non-classical MOS devices.
author2 Zhou Xing
author_facet Zhou Xing
See, Guan Huei
format Theses and Dissertations
author See, Guan Huei
author_sort See, Guan Huei
title Scalable compact modeling for nanometer CMOS technology
title_short Scalable compact modeling for nanometer CMOS technology
title_full Scalable compact modeling for nanometer CMOS technology
title_fullStr Scalable compact modeling for nanometer CMOS technology
title_full_unstemmed Scalable compact modeling for nanometer CMOS technology
title_sort scalable compact modeling for nanometer cmos technology
publishDate 2009
url https://hdl.handle.net/10356/18733
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