Delay sensitivity analysis of scaled BiCMOS/CMOS/ECL circuits

Delay sensitivity analysis of scaled BiCMOS/CMOS/ECL circuits

The speed sensitivity of the BiCMOS, CMOS and ECL inverter circuits to changes in the key MOS/BJT device parameters is analyzed. The study of BiCMOS circuit takes into account the changes in the forward transit time, the knee current, the collector resistance, the base resistance, and the current ga...

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Bibliographic Details
Main Author: Sin, You Seng.
Other Authors: Yeo, Kiat Seng
Format: Theses and Dissertations
Language:English
Published: 2009
Subjects:
DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
Online Access:http://hdl.handle.net/10356/19686
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Institution: Nanyang Technological University
Language: English
Description
Summary:The speed sensitivity of the BiCMOS, CMOS and ECL inverter circuits to changes in the key MOS/BJT device parameters is analyzed. The study of BiCMOS circuit takes into account the changes in the forward transit time, the knee current, the collector resistance, the base resistance, and the current gain of the bipolar transistor and the channel width and length, threshold voltage and the oxide thickness of the MOS transistor.

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