Delay sensitivity analysis of scaled BiCMOS/CMOS/ECL circuits

The speed sensitivity of the BiCMOS, CMOS and ECL inverter circuits to changes in the key MOS/BJT device parameters is analyzed. The study of BiCMOS circuit takes into account the changes in the forward transit time, the knee current, the collector resistance, the base resistance, and the current ga...

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Main Author:	Sin, You Seng.
Other Authors:	Yeo, Kiat Seng
Format:	Theses and Dissertations
Language:	English
Published:	2009
Subjects:	DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
Online Access:	http://hdl.handle.net/10356/19686
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Institution:	Nanyang Technological University
Language:	English

id	sg-ntu-dr.10356-19686
record_format	dspace
spelling	sg-ntu-dr.10356-196862023-07-04T15:32:15Z Delay sensitivity analysis of scaled BiCMOS/CMOS/ECL circuits Sin, You Seng. Yeo, Kiat Seng School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits The speed sensitivity of the BiCMOS, CMOS and ECL inverter circuits to changes in the key MOS/BJT device parameters is analyzed. The study of BiCMOS circuit takes into account the changes in the forward transit time, the knee current, the collector resistance, the base resistance, and the current gain of the bipolar transistor and the channel width and length, threshold voltage and the oxide thickness of the MOS transistor. Master of Engineering 2009-12-14T06:21:38Z 2009-12-14T06:21:38Z 1995 1995 Thesis http://hdl.handle.net/10356/19686 en NANYANG TECHNOLOGICAL UNIVERSITY 117 p. application/pdf
institution	Nanyang Technological University
building	NTU Library
continent	Asia
country	Singapore Singapore
content_provider	NTU Library
collection	DR-NTU
language	English
topic	DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
spellingShingle	DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits Sin, You Seng. Delay sensitivity analysis of scaled BiCMOS/CMOS/ECL circuits
description	The speed sensitivity of the BiCMOS, CMOS and ECL inverter circuits to changes in the key MOS/BJT device parameters is analyzed. The study of BiCMOS circuit takes into account the changes in the forward transit time, the knee current, the collector resistance, the base resistance, and the current gain of the bipolar transistor and the channel width and length, threshold voltage and the oxide thickness of the MOS transistor.
author2	Yeo, Kiat Seng
author_facet	Yeo, Kiat Seng Sin, You Seng.
format	Theses and Dissertations
author	Sin, You Seng.
author_sort	Sin, You Seng.
title	Delay sensitivity analysis of scaled BiCMOS/CMOS/ECL circuits
title_short	Delay sensitivity analysis of scaled BiCMOS/CMOS/ECL circuits
title_full	Delay sensitivity analysis of scaled BiCMOS/CMOS/ECL circuits
title_fullStr	Delay sensitivity analysis of scaled BiCMOS/CMOS/ECL circuits
title_full_unstemmed	Delay sensitivity analysis of scaled BiCMOS/CMOS/ECL circuits
title_sort	delay sensitivity analysis of scaled bicmos/cmos/ecl circuits
publishDate	2009
url	http://hdl.handle.net/10356/19686
_version_	1772825611255939072

Delay sensitivity analysis of scaled BiCMOS/CMOS/ECL circuits

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