Delay sensitivity analysis of scaled BiCMOS/CMOS/ECL circuits
The speed sensitivity of the BiCMOS, CMOS and ECL inverter circuits to changes in the key MOS/BJT device parameters is analyzed. The study of BiCMOS circuit takes into account the changes in the forward transit time, the knee current, the collector resistance, the base resistance, and the current ga...
Saved in:
Main Author: | Sin, You Seng. |
---|---|
Other Authors: | Yeo, Kiat Seng |
Format: | Theses and Dissertations |
Language: | English |
Published: |
2009
|
Subjects: | |
Online Access: | http://hdl.handle.net/10356/19686 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Institution: | Nanyang Technological University |
Language: | English |
Similar Items
-
Development of NTU CMOS process for SiGe BiCMOS technology
by: Wang, Jianpeng.
Published: (2008) -
Development of submicron BiCMOS digital library cells for ASIC applications
by: Do, Manh Anh, et al.
Published: (2008) -
Performance characterisation and design issues of low voltage BiCMOS digital circuits
by: Cheong, Chee Seng.
Published: (2008) -
Development of submicron BiCMOS/CMOS digital cell library for low-voltage low-power applications
by: Lee, Heng Kah.
Published: (2008) -
New BiCMOS device structures and circuits for low-voltage low-power applications
by: Yeo, Kiat Seng
Published: (2009)