Chemical and mechanical polishing for realization of advanced planarization schemes and patterned SOI structures

First part aimed at producing varied planarization schemes that are suitable for both the Shallow Trench Isolated test structures and the Static Random Access Memory structures. Second part, the direct-wafer bonding process was employed to arrive at the Silicon-On-Insulator substrates.

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Bibliographic Details
Main Authors:	Goh, Wang Ling., Tse, Man Siu.
Other Authors:	School of Electrical and Electronic Engineering
Format:	Research Report
Published:	2008
Subjects:	DRNTU::Engineering::Electrical and electronic engineering::Electronic packaging
Online Access:	http://hdl.handle.net/10356/2776
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Institution:	Nanyang Technological University

id	sg-ntu-dr.10356-2776
record_format	dspace
spelling	sg-ntu-dr.10356-27762023-03-04T03:19:45Z Chemical and mechanical polishing for realization of advanced planarization schemes and patterned SOI structures Goh, Wang Ling. Tse, Man Siu. School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Electronic packaging First part aimed at producing varied planarization schemes that are suitable for both the Shallow Trench Isolated test structures and the Static Random Access Memory structures. Second part, the direct-wafer bonding process was employed to arrive at the Silicon-On-Insulator substrates. RG 46/96 2008-09-17T09:14:34Z 2008-09-17T09:14:34Z 2001 2001 Research Report http://hdl.handle.net/10356/2776 Nanyang Technological University application/pdf
institution	Nanyang Technological University
building	NTU Library
continent	Asia
country	Singapore Singapore
content_provider	NTU Library
collection	DR-NTU
topic	DRNTU::Engineering::Electrical and electronic engineering::Electronic packaging
spellingShingle	DRNTU::Engineering::Electrical and electronic engineering::Electronic packaging Goh, Wang Ling. Tse, Man Siu. Chemical and mechanical polishing for realization of advanced planarization schemes and patterned SOI structures
description	First part aimed at producing varied planarization schemes that are suitable for both the Shallow Trench Isolated test structures and the Static Random Access Memory structures. Second part, the direct-wafer bonding process was employed to arrive at the Silicon-On-Insulator substrates.
author2	School of Electrical and Electronic Engineering
author_facet	School of Electrical and Electronic Engineering Goh, Wang Ling. Tse, Man Siu.
format	Research Report
author	Goh, Wang Ling. Tse, Man Siu.
author_sort	Goh, Wang Ling.
title	Chemical and mechanical polishing for realization of advanced planarization schemes and patterned SOI structures
title_short	Chemical and mechanical polishing for realization of advanced planarization schemes and patterned SOI structures
title_full	Chemical and mechanical polishing for realization of advanced planarization schemes and patterned SOI structures
title_fullStr	Chemical and mechanical polishing for realization of advanced planarization schemes and patterned SOI structures
title_full_unstemmed	Chemical and mechanical polishing for realization of advanced planarization schemes and patterned SOI structures
title_sort	chemical and mechanical polishing for realization of advanced planarization schemes and patterned soi structures
publishDate	2008
url	http://hdl.handle.net/10356/2776
_version_	1759853504697991168

Chemical and mechanical polishing for realization of advanced planarization schemes and patterned SOI structures

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