Chemical and mechanical polishing for realization of advanced planarization schemes and patterned SOI structures

• Main Authors: Goh, Wang Ling., Tse, Man Siu.
• Other Authors: School of Electrical and Electronic Engineering
• Format: Research Report
• Published: 2008
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Electronic packaging
• Online Access: http://hdl.handle.net/10356/2776
• Institution: Nanyang Technological University

First part aimed at producing varied planarization schemes that are suitable for both the Shallow Trench Isolated test structures and the Static Random Access Memory structures. Second part, the direct-wafer bonding process was employed to arrive at the Silicon-On-Insulator substrates.