Realization of trenched SOI structure using wafer bonding technique

• المؤلف الرئيسي: Teo, Kim Poh.
• مؤلفون آخرون: Goh, Wang Ling
• التنسيق: Theses and Dissertations
• منشور في: 2008
• الموضوعات: DRNTU::Engineering::Electrical and electronic engineering::Electronic packaging
• الوصول للمادة أونلاين: http://hdl.handle.net/10356/3559
• المؤسسة: Nanyang Technological University

In this project, the realization of a trenched SOI substrate is carried out, and the characterization of the CMP planarization together with a new polysilicon shallow trench isolation (STI) technique is studied.