Realization of trenched SOI structure using wafer bonding technique

• Main Author: Teo, Kim Poh.
• Other Authors: Goh, Wang Ling
• Format: Theses and Dissertations
• Published: 2008
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Electronic packaging
• Online Access: http://hdl.handle.net/10356/3559
• Institution: Nanyang Technological University

In this project, the realization of a trenched SOI substrate is carried out, and the characterization of the CMP planarization together with a new polysilicon shallow trench isolation (STI) technique is studied.