Asynchronous pipelined macrocell design for high speed digital applications
Since the beginning of the digital era, synchronous methodology has overtaken digital system design for its simplicity in implementation. The synchronous global clock, however, may become a major problem as technology scales. This rekindles the interest of asynchronous design methodology, which has...
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| Format: | Theses and Dissertations |
| Published: |
2008
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| Online Access: | http://hdl.handle.net/10356/3265 |
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| Institution: | Nanyang Technological University |
| Summary: | Since the beginning of the digital era, synchronous methodology has overtaken digital system design for its simplicity in implementation. The synchronous global clock, however, may become a major problem as technology scales. This rekindles the interest of asynchronous design methodology, which has long been losing its edge because of relatively more subtle design concepts and associative circuit overhead due to extra control (handshake) signaling. |
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