Asynchronous pipelined macrocell design for high speed digital applications

Asynchronous pipelined macrocell design for high speed digital applications

Since the beginning of the digital era, synchronous methodology has overtaken digital system design for its simplicity in implementation. The synchronous global clock, however, may become a major problem as technology scales. This rekindles the interest of asynchronous design methodology, which has...

Full description

Saved in:
Bibliographic Details
Main Author: Sin, Tze Yee.
Other Authors: Wong, Eddie Moon Chung
Format: Theses and Dissertations
Published: 2008
Subjects:
DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Online Access:http://hdl.handle.net/10356/3265
Tags: Add Tag
No Tags, Be the first to tag this record!
Institution: Nanyang Technological University
id sg-ntu-dr.10356-3265
record_format dspace
spelling sg-ntu-dr.10356-32652023-07-04T15:17:55Z Asynchronous pipelined macrocell design for high speed digital applications Sin, Tze Yee. Wong, Eddie Moon Chung School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits Since the beginning of the digital era, synchronous methodology has overtaken digital system design for its simplicity in implementation. The synchronous global clock, however, may become a major problem as technology scales. This rekindles the interest of asynchronous design methodology, which has long been losing its edge because of relatively more subtle design concepts and associative circuit overhead due to extra control (handshake) signaling. Master of Engineering 2008-09-17T09:25:54Z 2008-09-17T09:25:54Z 2003 2003 Thesis http://hdl.handle.net/10356/3265 Nanyang Technological University application/pdf
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
topic DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
spellingShingle DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Sin, Tze Yee.
Asynchronous pipelined macrocell design for high speed digital applications
description Since the beginning of the digital era, synchronous methodology has overtaken digital system design for its simplicity in implementation. The synchronous global clock, however, may become a major problem as technology scales. This rekindles the interest of asynchronous design methodology, which has long been losing its edge because of relatively more subtle design concepts and associative circuit overhead due to extra control (handshake) signaling.
author2 Wong, Eddie Moon Chung
author_facet Wong, Eddie Moon Chung
Sin, Tze Yee.
format Theses and Dissertations
author Sin, Tze Yee.
author_sort Sin, Tze Yee.
title Asynchronous pipelined macrocell design for high speed digital applications
title_short Asynchronous pipelined macrocell design for high speed digital applications
title_full Asynchronous pipelined macrocell design for high speed digital applications
title_fullStr Asynchronous pipelined macrocell design for high speed digital applications
title_full_unstemmed Asynchronous pipelined macrocell design for high speed digital applications
title_sort asynchronous pipelined macrocell design for high speed digital applications
publishDate 2008
url http://hdl.handle.net/10356/3265
_version_ 1772827888263888896

Similar Items