Source line resistance failure issues and process optimisation of self aligned source etch
A self-aligned source oxide etch recipe using low power recipe was changed to higher power recipe to improve production cycle time (due to higher etch rate) and resolve plasma un-ignition. However, some lots started to fail with higher source line resistance during electrical testing.
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sg-ntu-dr.10356-32972023-07-04T16:05:38Z Source line resistance failure issues and process optimisation of self aligned source etch Su, Julia Hui Fong. Prasad, Krishnamachar School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Microelectronics A self-aligned source oxide etch recipe using low power recipe was changed to higher power recipe to improve production cycle time (due to higher etch rate) and resolve plasma un-ignition. However, some lots started to fail with higher source line resistance during electrical testing. Master of Science (Microelectronics) 2008-09-17T09:26:47Z 2008-09-17T09:26:47Z 2004 2004 Thesis http://hdl.handle.net/10356/3297 Nanyang Technological University application/pdf |
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DRNTU::Engineering::Electrical and electronic engineering::Microelectronics Su, Julia Hui Fong. Source line resistance failure issues and process optimisation of self aligned source etch |
description |
A self-aligned source oxide etch recipe using low power recipe was changed to higher power recipe to improve production cycle time (due to higher etch rate) and resolve plasma un-ignition. However, some lots started to fail with higher source line resistance during electrical testing. |
author2 |
Prasad, Krishnamachar |
author_facet |
Prasad, Krishnamachar Su, Julia Hui Fong. |
format |
Theses and Dissertations |
author |
Su, Julia Hui Fong. |
author_sort |
Su, Julia Hui Fong. |
title |
Source line resistance failure issues and process optimisation of self aligned source etch |
title_short |
Source line resistance failure issues and process optimisation of self aligned source etch |
title_full |
Source line resistance failure issues and process optimisation of self aligned source etch |
title_fullStr |
Source line resistance failure issues and process optimisation of self aligned source etch |
title_full_unstemmed |
Source line resistance failure issues and process optimisation of self aligned source etch |
title_sort |
source line resistance failure issues and process optimisation of self aligned source etch |
publishDate |
2008 |
url |
http://hdl.handle.net/10356/3297 |
_version_ |
1772826120932032512 |