Resolving p-type transistor drain saturation current (IDsat) off-target issue for 0.3um logic device
Transistor optimization is required for good device performance especially on those devices with off-center electrical se (ET) specifications. In this thesis, the author explores various possible options to bring a particular 0.3?m device Logic Dual gate oxide PMOS transistor IDsat to electrical tes...
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格式: | Theses and Dissertations |
出版: |
2008
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在線閱讀: | http://hdl.handle.net/10356/3325 |
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機構: | Nanyang Technological University |